mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX  147 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX                                                           0
mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX  150 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX                                                           0