mmUVD_JRBC_ENC_RB_WPTR  164 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_JRBC_ENC_RB_WPTR                                                                         0x0120
mmUVD_JRBC_ENC_RB_WPTR  167 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_JRBC_ENC_RB_WPTR                                                                         0x0120