mmUVD_JRBC_ENC_RB_COND_RD_TIMER  174 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER                                                                0x0125
mmUVD_JRBC_ENC_RB_COND_RD_TIMER  177 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER                                                                0x0125