mmUVD_GPCOM_VCPU_CMD_BASE_IDX   55 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX                                                                  1
mmUVD_GPCOM_VCPU_CMD_BASE_IDX  139 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX                                                                  1
mmUVD_GPCOM_VCPU_CMD_BASE_IDX  811 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX                                                                  1
mmUVD_GPCOM_VCPU_CMD_BASE_IDX  500 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX                                                                  1