mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX   47 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX                                                          1
mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX   77 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX                                                          1
mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX  437 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX                                                          1
mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX  440 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX                                                          1