mmUVD_DPG_PAUSE_BASE_IDX   43 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_DPG_PAUSE_BASE_IDX                                                                       1
mmUVD_DPG_PAUSE_BASE_IDX  401 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_DPG_PAUSE_BASE_IDX                                                                       1
mmUVD_DPG_PAUSE_BASE_IDX  404 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_DPG_PAUSE_BASE_IDX                                                                       1