mmUVD_DPG_PAUSE 42 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_DPG_PAUSE 0x00d4 mmUVD_DPG_PAUSE 400 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_DPG_PAUSE 0x0014 mmUVD_DPG_PAUSE 403 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_DPG_PAUSE 0x0014