mmUVD_DPG_LMA_MASK_BASE_IDX   41 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_DPG_LMA_MASK_BASE_IDX                                                                    1
mmUVD_DPG_LMA_MASK_BASE_IDX  399 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_DPG_LMA_MASK_BASE_IDX                                                                    1
mmUVD_DPG_LMA_MASK_BASE_IDX  402 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_DPG_LMA_MASK_BASE_IDX                                                                    1