mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX  767 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX  567 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX  205 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX  219 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1