mmSQ_UTCL1_CNTL2_BASE_IDX  421 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSQ_UTCL1_CNTL2_BASE_IDX                                                                      0
mmSQ_UTCL1_CNTL2_BASE_IDX  415 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSQ_UTCL1_CNTL2_BASE_IDX                                                                      0
mmSQ_UTCL1_CNTL2_BASE_IDX  411 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSQ_UTCL1_CNTL2_BASE_IDX                                                                      0