mmSQ_UTCL1_CNTL1_BASE_IDX  419 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSQ_UTCL1_CNTL1_BASE_IDX                                                                      0
mmSQ_UTCL1_CNTL1_BASE_IDX  413 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSQ_UTCL1_CNTL1_BASE_IDX                                                                      0
mmSQ_UTCL1_CNTL1_BASE_IDX  409 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSQ_UTCL1_CNTL1_BASE_IDX                                                                      0