mmSQ_UTCL1_CNTL1  418 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSQ_UTCL1_CNTL1                                                                               0x0317
mmSQ_UTCL1_CNTL1  412 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSQ_UTCL1_CNTL1                                                                               0x0317
mmSQ_UTCL1_CNTL1  408 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSQ_UTCL1_CNTL1                                                                               0x0317