mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX 2457 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX                                                               0
mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX  417 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX                                                               0
mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX  411 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX                                                               0
mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX  407 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX                                                               0