mmSQ_DSM_CNTL_BASE_IDX 2437 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSQ_DSM_CNTL_BASE_IDX                                                                         0
mmSQ_DSM_CNTL_BASE_IDX  401 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSQ_DSM_CNTL_BASE_IDX                                                                         0
mmSQ_DSM_CNTL_BASE_IDX  395 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSQ_DSM_CNTL_BASE_IDX                                                                         0
mmSQ_DSM_CNTL_BASE_IDX  391 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSQ_DSM_CNTL_BASE_IDX                                                                         0