mmSQ_DSM_CNTL2_BASE_IDX 2439 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSQ_DSM_CNTL2_BASE_IDX                                                                        0
mmSQ_DSM_CNTL2_BASE_IDX  403 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSQ_DSM_CNTL2_BASE_IDX                                                                        0
mmSQ_DSM_CNTL2_BASE_IDX  397 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSQ_DSM_CNTL2_BASE_IDX                                                                        0
mmSQ_DSM_CNTL2_BASE_IDX  393 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSQ_DSM_CNTL2_BASE_IDX                                                                        0