mmSQC_DSM_CNTL_BASE_IDX  433 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSQC_DSM_CNTL_BASE_IDX                                                                        0
mmSQC_DSM_CNTL_BASE_IDX  427 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSQC_DSM_CNTL_BASE_IDX                                                                        0
mmSQC_DSM_CNTL_BASE_IDX  423 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSQC_DSM_CNTL_BASE_IDX                                                                        0