mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX  655 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX                                                              0
mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX  649 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX                                                              0
mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX  627 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX                                                              0