mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX  653 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX                                                              0
mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX  647 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX                                                              0
mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX  625 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX                                                              0