mmSPI_PS_INPUT_CNTL_9_BASE_IDX 6259 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSPI_PS_INPUT_CNTL_9_BASE_IDX                                                                 1
mmSPI_PS_INPUT_CNTL_9_BASE_IDX 3853 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSPI_PS_INPUT_CNTL_9_BASE_IDX                                                                 1
mmSPI_PS_INPUT_CNTL_9_BASE_IDX 4105 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSPI_PS_INPUT_CNTL_9_BASE_IDX                                                                 1
mmSPI_PS_INPUT_CNTL_9_BASE_IDX 4057 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSPI_PS_INPUT_CNTL_9_BASE_IDX                                                                 1