mmSPI_PS_INPUT_CNTL_8_BASE_IDX 6257 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSPI_PS_INPUT_CNTL_8_BASE_IDX                                                                 1
mmSPI_PS_INPUT_CNTL_8_BASE_IDX 3851 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSPI_PS_INPUT_CNTL_8_BASE_IDX                                                                 1
mmSPI_PS_INPUT_CNTL_8_BASE_IDX 4103 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSPI_PS_INPUT_CNTL_8_BASE_IDX                                                                 1
mmSPI_PS_INPUT_CNTL_8_BASE_IDX 4055 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSPI_PS_INPUT_CNTL_8_BASE_IDX                                                                 1