mmSPI_PS_INPUT_CNTL_5_BASE_IDX 6251 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSPI_PS_INPUT_CNTL_5_BASE_IDX                                                                 1
mmSPI_PS_INPUT_CNTL_5_BASE_IDX 3845 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSPI_PS_INPUT_CNTL_5_BASE_IDX                                                                 1
mmSPI_PS_INPUT_CNTL_5_BASE_IDX 4097 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSPI_PS_INPUT_CNTL_5_BASE_IDX                                                                 1
mmSPI_PS_INPUT_CNTL_5_BASE_IDX 4049 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSPI_PS_INPUT_CNTL_5_BASE_IDX                                                                 1