mmSPI_PS_INPUT_CNTL_28_BASE_IDX 6297 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSPI_PS_INPUT_CNTL_28_BASE_IDX                                                                1
mmSPI_PS_INPUT_CNTL_28_BASE_IDX 3891 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSPI_PS_INPUT_CNTL_28_BASE_IDX                                                                1
mmSPI_PS_INPUT_CNTL_28_BASE_IDX 4143 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSPI_PS_INPUT_CNTL_28_BASE_IDX                                                                1
mmSPI_PS_INPUT_CNTL_28_BASE_IDX 4095 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSPI_PS_INPUT_CNTL_28_BASE_IDX                                                                1