mmSPI_PS_INPUT_CNTL_25_BASE_IDX 6291 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSPI_PS_INPUT_CNTL_25_BASE_IDX                                                                1
mmSPI_PS_INPUT_CNTL_25_BASE_IDX 3885 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSPI_PS_INPUT_CNTL_25_BASE_IDX                                                                1
mmSPI_PS_INPUT_CNTL_25_BASE_IDX 4137 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSPI_PS_INPUT_CNTL_25_BASE_IDX                                                                1
mmSPI_PS_INPUT_CNTL_25_BASE_IDX 4089 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSPI_PS_INPUT_CNTL_25_BASE_IDX                                                                1