mmSPI_PS_INPUT_CNTL_21 6282 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSPI_PS_INPUT_CNTL_21                                                                         0x01a6
mmSPI_PS_INPUT_CNTL_21 3876 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSPI_PS_INPUT_CNTL_21                                                                         0x01a6
mmSPI_PS_INPUT_CNTL_21 4128 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSPI_PS_INPUT_CNTL_21                                                                         0x01a6
mmSPI_PS_INPUT_CNTL_21 4080 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSPI_PS_INPUT_CNTL_21                                                                         0x01a6
mmSPI_PS_INPUT_CNTL_21 1234 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h #define mmSPI_PS_INPUT_CNTL_21 0xA1A6
mmSPI_PS_INPUT_CNTL_21 1382 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmSPI_PS_INPUT_CNTL_21                                                  0xa1a6
mmSPI_PS_INPUT_CNTL_21 1399 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmSPI_PS_INPUT_CNTL_21                                                  0xa1a6
mmSPI_PS_INPUT_CNTL_21 1578 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmSPI_PS_INPUT_CNTL_21                                                  0xa1a6
mmSPI_PS_INPUT_CNTL_21 1546 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmSPI_PS_INPUT_CNTL_21                                                  0xa1a6