mmSPI_PS_INPUT_CNTL_20 6280 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSPI_PS_INPUT_CNTL_20                                                                         0x01a5
mmSPI_PS_INPUT_CNTL_20 3874 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSPI_PS_INPUT_CNTL_20                                                                         0x01a5
mmSPI_PS_INPUT_CNTL_20 4126 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSPI_PS_INPUT_CNTL_20                                                                         0x01a5
mmSPI_PS_INPUT_CNTL_20 4078 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSPI_PS_INPUT_CNTL_20                                                                         0x01a5
mmSPI_PS_INPUT_CNTL_20 1232 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h #define mmSPI_PS_INPUT_CNTL_20 0xA1A5
mmSPI_PS_INPUT_CNTL_20 1381 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmSPI_PS_INPUT_CNTL_20                                                  0xa1a5
mmSPI_PS_INPUT_CNTL_20 1398 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmSPI_PS_INPUT_CNTL_20                                                  0xa1a5
mmSPI_PS_INPUT_CNTL_20 1577 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmSPI_PS_INPUT_CNTL_20                                                  0xa1a5
mmSPI_PS_INPUT_CNTL_20 1545 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmSPI_PS_INPUT_CNTL_20                                                  0xa1a5