mmSPI_PS_INPUT_CNTL_15_BASE_IDX 6271 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSPI_PS_INPUT_CNTL_15_BASE_IDX                                                                1
mmSPI_PS_INPUT_CNTL_15_BASE_IDX 3865 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSPI_PS_INPUT_CNTL_15_BASE_IDX                                                                1
mmSPI_PS_INPUT_CNTL_15_BASE_IDX 4117 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSPI_PS_INPUT_CNTL_15_BASE_IDX                                                                1
mmSPI_PS_INPUT_CNTL_15_BASE_IDX 4069 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSPI_PS_INPUT_CNTL_15_BASE_IDX                                                                1