mmSPI_PS_INPUT_CNTL_15 6270 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSPI_PS_INPUT_CNTL_15                                                                         0x01a0
mmSPI_PS_INPUT_CNTL_15 3864 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSPI_PS_INPUT_CNTL_15                                                                         0x01a0
mmSPI_PS_INPUT_CNTL_15 4116 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSPI_PS_INPUT_CNTL_15                                                                         0x01a0
mmSPI_PS_INPUT_CNTL_15 4068 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSPI_PS_INPUT_CNTL_15                                                                         0x01a0
mmSPI_PS_INPUT_CNTL_15 1227 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h #define mmSPI_PS_INPUT_CNTL_15 0xA1A0
mmSPI_PS_INPUT_CNTL_15 1376 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmSPI_PS_INPUT_CNTL_15                                                  0xa1a0
mmSPI_PS_INPUT_CNTL_15 1393 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmSPI_PS_INPUT_CNTL_15                                                  0xa1a0
mmSPI_PS_INPUT_CNTL_15 1572 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmSPI_PS_INPUT_CNTL_15                                                  0xa1a0
mmSPI_PS_INPUT_CNTL_15 1540 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmSPI_PS_INPUT_CNTL_15                                                  0xa1a0