mmSPI_PS_INPUT_CNTL_0_BASE_IDX 6241 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSPI_PS_INPUT_CNTL_0_BASE_IDX                                                                 1
mmSPI_PS_INPUT_CNTL_0_BASE_IDX 3835 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSPI_PS_INPUT_CNTL_0_BASE_IDX                                                                 1
mmSPI_PS_INPUT_CNTL_0_BASE_IDX 4087 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSPI_PS_INPUT_CNTL_0_BASE_IDX                                                                 1
mmSPI_PS_INPUT_CNTL_0_BASE_IDX 4039 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSPI_PS_INPUT_CNTL_0_BASE_IDX                                                                 1