mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 2713 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX                                                          0
mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX  813 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX                                                          0
mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX  787 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX                                                          0
mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX  763 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX                                                          0