mmSPI_DSM_CNTL_BASE_IDX 2589 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSPI_DSM_CNTL_BASE_IDX                                                                        0
mmSPI_DSM_CNTL_BASE_IDX  685 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmSPI_DSM_CNTL_BASE_IDX                                                                        0
mmSPI_DSM_CNTL_BASE_IDX  667 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmSPI_DSM_CNTL_BASE_IDX                                                                        0
mmSPI_DSM_CNTL_BASE_IDX  645 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmSPI_DSM_CNTL_BASE_IDX                                                                        0