mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX  553 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX  197 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX  211 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1