mmSMU_INTERRUPT_CONTROL_BASE_IDX  737 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmSMU_INTERRUPT_CONTROL_BASE_IDX                                                               1
mmSMU_INTERRUPT_CONTROL_BASE_IDX  935 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
mmSMU_INTERRUPT_CONTROL_BASE_IDX  601 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
mmSMU_INTERRUPT_CONTROL_BASE_IDX  563 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2