mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX  858 drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h #define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX                                                           0
mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 2495 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h #define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX                                                           2
mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 4377 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h #define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX                                                           2