mmSMU_BIF_VDDGFX_PWR_STATUS  103 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h #define mmSMU_BIF_VDDGFX_PWR_STATUS                                             0x14f8
mmSMU_BIF_VDDGFX_PWR_STATUS   95 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h #define mmSMU_BIF_VDDGFX_PWR_STATUS                                             0x14f8
mmSMU_BIF_VDDGFX_PWR_STATUS  857 drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h #define mmSMU_BIF_VDDGFX_PWR_STATUS                                                                    0x0e33 // duplicate 
mmSMU_BIF_VDDGFX_PWR_STATUS 2494 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h #define mmSMU_BIF_VDDGFX_PWR_STATUS                                                                    0x0113
mmSMU_BIF_VDDGFX_PWR_STATUS 4376 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h #define mmSMU_BIF_VDDGFX_PWR_STATUS                                                                    0x0113