mmSMBUS_BLKWR_CMD_CTRL1_BASE_IDX  217 drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h #define mmSMBUS_BLKWR_CMD_CTRL1_BASE_IDX                                                               0
mmSMBUS_BLKWR_CMD_CTRL1_BASE_IDX  299 drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_offset.h #define mmSMBUS_BLKWR_CMD_CTRL1_BASE_IDX                                                               0