mmSMBUS_BLKWR_CMD_CTRL0  214 drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h #define mmSMBUS_BLKWR_CMD_CTRL0                                                                        0x009b
mmSMBUS_BLKWR_CMD_CTRL0  296 drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_offset.h #define mmSMBUS_BLKWR_CMD_CTRL0                                                                        0x009b