mmSEM_MAILBOX_CONTROL_BASE_IDX  259 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_offset.h #define mmSEM_MAILBOX_CONTROL_BASE_IDX                                                                 0
mmSEM_MAILBOX_CONTROL_BASE_IDX  259 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_offset.h #define mmSEM_MAILBOX_CONTROL_BASE_IDX                                                                 0
mmSEM_MAILBOX_CONTROL_BASE_IDX  271 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_offset.h #define mmSEM_MAILBOX_CONTROL_BASE_IDX                                                                 0