mmSDMA1_UTCL1_WR_STATUS 1111 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA1_UTCL1_WR_STATUS                                                                        0x063f
mmSDMA1_UTCL1_WR_STATUS  132 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h #define mmSDMA1_UTCL1_WR_STATUS	0x003f
mmSDMA1_UTCL1_WR_STATUS  132 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h #define mmSDMA1_UTCL1_WR_STATUS                                                                        0x003f
mmSDMA1_UTCL1_WR_STATUS  132 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h #define mmSDMA1_UTCL1_WR_STATUS                                                                        0x003f