mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1879 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX  889 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h #define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX  885 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h #define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0