mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 1836 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x0952
mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI  846 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x031a
mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI  842 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x0352