mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1843 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         0
mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX  853 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h #define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         0
mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX  849 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h #define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         0