mmSDMA1_RLC3_RB_WPTR_POLL_CNTL 1629 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL                                                                 0x0867
mmSDMA1_RLC3_RB_WPTR_POLL_CNTL  636 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h #define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL                                                                 0x023f
mmSDMA1_RLC3_RB_WPTR_POLL_CNTL  632 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h #define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL                                                                 0x0267