mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 1670 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x0892
mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI  678 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x026a
mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI  674 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x0292