mmSDMA1_RLC0_RB_WPTR_HI 1378 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA1_RLC0_RB_WPTR_HI                                                                        0x0746
mmSDMA1_RLC0_RB_WPTR_HI  382 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h #define mmSDMA1_RLC0_RB_WPTR_HI	0x0146
mmSDMA1_RLC0_RB_WPTR_HI  382 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h #define mmSDMA1_RLC0_RB_WPTR_HI                                                                        0x0136
mmSDMA1_RLC0_RB_WPTR_HI  378 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h #define mmSDMA1_RLC0_RB_WPTR_HI                                                                        0x0146