mmSDMA1_PHASE1_QUANTUM_BASE_IDX 1084 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA1_PHASE1_QUANTUM_BASE_IDX                                                                0
mmSDMA1_PHASE1_QUANTUM_BASE_IDX  105 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h #define mmSDMA1_PHASE1_QUANTUM_BASE_IDX	0
mmSDMA1_PHASE1_QUANTUM_BASE_IDX  105 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h #define mmSDMA1_PHASE1_QUANTUM_BASE_IDX                                                                0
mmSDMA1_PHASE1_QUANTUM_BASE_IDX  105 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h #define mmSDMA1_PHASE1_QUANTUM_BASE_IDX                                                                0