mmSDMA1_PHASE1_QUANTUM 1083 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA1_PHASE1_QUANTUM                                                                         0x062d
mmSDMA1_PHASE1_QUANTUM  335 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h #define mmSDMA1_PHASE1_QUANTUM                                                  0x3615
mmSDMA1_PHASE1_QUANTUM  290 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h #define mmSDMA1_PHASE1_QUANTUM                                                  0x3615
mmSDMA1_PHASE1_QUANTUM  350 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h #define mmSDMA1_PHASE1_QUANTUM                                                  0x3615
mmSDMA1_PHASE1_QUANTUM  466 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h #define mmSDMA1_PHASE1_QUANTUM                                                  0x3615
mmSDMA1_PHASE1_QUANTUM  104 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h #define mmSDMA1_PHASE1_QUANTUM	0x002d
mmSDMA1_PHASE1_QUANTUM  104 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h #define mmSDMA1_PHASE1_QUANTUM                                                                         0x002d
mmSDMA1_PHASE1_QUANTUM  104 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h #define mmSDMA1_PHASE1_QUANTUM                                                                         0x002d