mmSDMA1_PHASE0_QUANTUM 1081 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA1_PHASE0_QUANTUM                                                                         0x062c
mmSDMA1_PHASE0_QUANTUM  334 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h #define mmSDMA1_PHASE0_QUANTUM                                                  0x3614
mmSDMA1_PHASE0_QUANTUM  289 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h #define mmSDMA1_PHASE0_QUANTUM                                                  0x3614
mmSDMA1_PHASE0_QUANTUM  349 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h #define mmSDMA1_PHASE0_QUANTUM                                                  0x3614
mmSDMA1_PHASE0_QUANTUM  465 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h #define mmSDMA1_PHASE0_QUANTUM                                                  0x3614
mmSDMA1_PHASE0_QUANTUM  102 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h #define mmSDMA1_PHASE0_QUANTUM	0x002c
mmSDMA1_PHASE0_QUANTUM  102 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h #define mmSDMA1_PHASE0_QUANTUM                                                                         0x002c
mmSDMA1_PHASE0_QUANTUM  102 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h #define mmSDMA1_PHASE0_QUANTUM                                                                         0x002c