mmSDMA1_GFX_RB_WPTR_POLL_CNTL 1212 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                                                  0x0687
mmSDMA1_GFX_RB_WPTR_POLL_CNTL  342 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                           0x3685
mmSDMA1_GFX_RB_WPTR_POLL_CNTL  301 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                           0x3685
mmSDMA1_GFX_RB_WPTR_POLL_CNTL  390 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                           0x3685
mmSDMA1_GFX_RB_WPTR_POLL_CNTL  494 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                           0x3685
mmSDMA1_GFX_RB_WPTR_POLL_CNTL  214 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL	0x0087
mmSDMA1_GFX_RB_WPTR_POLL_CNTL  214 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087
mmSDMA1_GFX_RB_WPTR_POLL_CNTL  210 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087