mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX  127 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX                                                               0
mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX  155 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX	0
mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX  153 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX                                                               0
mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX  155 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX                                                               0
mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX  155 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX                                                               0