mmSDMA0_UTCL1_WR_STATUS  112 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_UTCL1_WR_STATUS                                                                        0x003f
mmSDMA0_UTCL1_WR_STATUS  140 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_UTCL1_WR_STATUS	0x003f
mmSDMA0_UTCL1_WR_STATUS  138 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_UTCL1_WR_STATUS                                                                        0x003f
mmSDMA0_UTCL1_WR_STATUS  140 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_UTCL1_WR_STATUS                                                                        0x003f
mmSDMA0_UTCL1_WR_STATUS  140 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_UTCL1_WR_STATUS                                                                        0x003f